SUMMARY A new pipeline controller based on the Early Acknowl-edgement (EA) protocol is proposed for bundled-data asynchronous cir-cuits. The EA protocol indicates acknowledgement by the falling edge of the acknowledgement signal in contrast to the 4-phase protocol, which in-dicates it on the rising edge. Thus, it can hide the overhead caused by the resetting period of the handshake cycle. Since we have designed our controller assuming several timing constraints, we first analyze the tim-ing constraints under which our controller correctly works and then dis-cuss their appropriateness. The performance of the controller is compared both analytically and experimentally with those of two other pipeline con-trollers, namely, a very high-speed 2-...
An asynchronous pipeline circuit includes: a first processing stage including a first data latch con...
In this paper, we present a novel synchronization approach to support data flow in clockless designs...
Pipelining is a promising technique to deal with long delays in control loops, for instance due to i...
Over the past couple of decades, the digital design technology scales to date remarkably satisfying ...
International audienceThis paper presents two new area-reduced controllers for bundled-data asynchro...
In this paper, we present a novel synchronization approach to support data flow in clockless designs...
In previous work, a pipelined controller had been proposed, which enable better control methods to b...
Pipelining is a common method for improving the throughput of a system, especially when the majority...
In this paper, we present a novel synchronization approach to support data flow in clockless designs...
Journal ArticleA complete family of untimed asynchronous 4-phase pipeline protocols is derived and c...
In this paper, we present a new low-latency asynchronous pipeline control circuit. The control circu...
De-synchronization appears as a new paradigm to automate the design of asynchronous circuits from sy...
This paper presents a survey on high-throughput and ultra low-power asynchronous pipeline design met...
The minimization of propagation delay between pipeline stages is very important in wave propagation ...
Modern, fast microprocessors are deeply pipelined to enhance their performance. Thus they cannot aff...
An asynchronous pipeline circuit includes: a first processing stage including a first data latch con...
In this paper, we present a novel synchronization approach to support data flow in clockless designs...
Pipelining is a promising technique to deal with long delays in control loops, for instance due to i...
Over the past couple of decades, the digital design technology scales to date remarkably satisfying ...
International audienceThis paper presents two new area-reduced controllers for bundled-data asynchro...
In this paper, we present a novel synchronization approach to support data flow in clockless designs...
In previous work, a pipelined controller had been proposed, which enable better control methods to b...
Pipelining is a common method for improving the throughput of a system, especially when the majority...
In this paper, we present a novel synchronization approach to support data flow in clockless designs...
Journal ArticleA complete family of untimed asynchronous 4-phase pipeline protocols is derived and c...
In this paper, we present a new low-latency asynchronous pipeline control circuit. The control circu...
De-synchronization appears as a new paradigm to automate the design of asynchronous circuits from sy...
This paper presents a survey on high-throughput and ultra low-power asynchronous pipeline design met...
The minimization of propagation delay between pipeline stages is very important in wave propagation ...
Modern, fast microprocessors are deeply pipelined to enhance their performance. Thus they cannot aff...
An asynchronous pipeline circuit includes: a first processing stage including a first data latch con...
In this paper, we present a novel synchronization approach to support data flow in clockless designs...
Pipelining is a promising technique to deal with long delays in control loops, for instance due to i...