Abstract—Task scheduling is an important aspect of high performance reconfigurable computing. Most of the heuristics for this NP-hard problem are based on a simple abstract model of FPGA and have little investigation into optimizing data communication which influences the system performance importantly. To solve this problem, a Communication-aware Maximum Adjacent Edges (CA-MAE) algorithm based on new 2D reconfigurable model is proposed, which could reduce communication distance during scheduling and enhance the system performance. The experimental results show that CA-MAE reduces communication cost by 17%. Index Terms—reconfigurable computing, scheduling model, scheduling algorithm, communication time I
In this dissertation, we focus our research on the problems related to efficient configurable resour...
International audienceThe management of a reconfigurable resource included in a System-on-Chip is a ...
Partial reconfiguration allows for mapping and executing several tasks on an FPGA during run time. O...
High-performance reconfigurable computing involves acceleration of significant portions of an ap-pli...
Abstract—Reconfigurable Computers (RC) can provide signif-icant performance improvement for domain a...
In this paper we present a novel scheduling technique for partially-reconfigurable FPGA-based system...
This paper is motivated by existing architectures of field programmable gate arrays (FPGAs). To faci...
Real-time scheduling for FPGAs presents unique challenges to traditional real-time scheduling theory...
International audienceThis paper deals with the mathematical modelling of a scheduling problem in a ...
Reconfigurable Computers (RC) can provide significant performance improvement for domain application...
International audienceThis paper deals with the mathematical modelling of a scheduling problem in a ...
In reconfigurable computing systems, full reconfigurable FPGA are evolving rapidly, due to their fle...
By utilizing massively parallel circuit design in FPGAs, the overall system efficiency, in terms of ...
FPGAs are widely used in today's embedded systems design due to their low cost, high performance, an...
ARM-FPGA coupled platforms allow accelerating the computation of specific algorithms by executing th...
In this dissertation, we focus our research on the problems related to efficient configurable resour...
International audienceThe management of a reconfigurable resource included in a System-on-Chip is a ...
Partial reconfiguration allows for mapping and executing several tasks on an FPGA during run time. O...
High-performance reconfigurable computing involves acceleration of significant portions of an ap-pli...
Abstract—Reconfigurable Computers (RC) can provide signif-icant performance improvement for domain a...
In this paper we present a novel scheduling technique for partially-reconfigurable FPGA-based system...
This paper is motivated by existing architectures of field programmable gate arrays (FPGAs). To faci...
Real-time scheduling for FPGAs presents unique challenges to traditional real-time scheduling theory...
International audienceThis paper deals with the mathematical modelling of a scheduling problem in a ...
Reconfigurable Computers (RC) can provide significant performance improvement for domain application...
International audienceThis paper deals with the mathematical modelling of a scheduling problem in a ...
In reconfigurable computing systems, full reconfigurable FPGA are evolving rapidly, due to their fle...
By utilizing massively parallel circuit design in FPGAs, the overall system efficiency, in terms of ...
FPGAs are widely used in today's embedded systems design due to their low cost, high performance, an...
ARM-FPGA coupled platforms allow accelerating the computation of specific algorithms by executing th...
In this dissertation, we focus our research on the problems related to efficient configurable resour...
International audienceThe management of a reconfigurable resource included in a System-on-Chip is a ...
Partial reconfiguration allows for mapping and executing several tasks on an FPGA during run time. O...