Mathematical Programming Models for Scheduling in a CPU/FPGA Architecture with Communication Delay

International audienceThis paper deals with the mathematical modelling of a scheduling problem in a heterogeneous CPU/FPGA architecture with communication delay in order to minimize the makespan, Cmax. This study was motivated by the quality of the available solvers for Mixed Integer Program. The proposed model includes the communication delay constraints in a general form in a heterogeneous case depending at the same time on tasks and computing units. These constraints are linearized without adding any extra variables and the obtained linear model is reduced to make its solving with Cplex 12.5x faster. Computational results show that the proposed model is promising. For an average sized problem up to 50 tasks and 5 computing units the solving time under Cplex is about few seconds