In this paper, we overview general hardware architecture and a programming model of SRC-6ETM reconfigurable computers, and compare the performance of the SRC-6E machine vs. Intel ® Pentium IVTM. SRC-6E execution time measurements have been performed using three different approaches. In the first approach, the entire end-to-end execution time is taken into account. In the second approach, the configuration time of FPGAs have been omitted. In the third approach both configuration and data transfer overheads have been omitted. All measurements have been done for different numbers of data blocks. The results show that the SRC-6E can outperform a general-purpose microprocessor for computationally intensive algorithms by a factor of over 1500. Ho...
Reconfigurable Computers (RC) can provide significant performance improvement for domain application...
FPGA based systems have been heavily used to prototype and test Application Specic Integrated Cir...
In this case study, various ways to partition a code between the microprocessor and FPGA are examine...
Reconfigurable computing offers the promise of performing computations in hardware to increase perfo...
Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable ha...
Sorting is perhaps the most widely studied problem in computer science and is frequently used as a b...
The execution speed of the FPGA processing elements are compared to the microprocessor processing el...
n the past few years, high-performance computing vendors have introduced many systems contain-ing bo...
For last few decades, reconfigurable devices have been extensively used in digital systems. Reconfig...
The combination of traditional microprocessors workstations and hardware-reconfigurable Field Progra...
Run-Time Reconfigured systems offer additional hardware resources to systems based on reconfigurable...
Summarization: Fine-grain reconfigurable devices suffer from the time needed to load the configurati...
Fine-grain reconfigurable devices suffer from the time needed to load the configuration bitstream. E...
Runtime reconfigurable systems built upon devices with partial reconfiguration can provide reduction...
The saturation of single-thread performance, along with the advent of the power wall, has resulted i...
Reconfigurable Computers (RC) can provide significant performance improvement for domain application...
FPGA based systems have been heavily used to prototype and test Application Specic Integrated Cir...
In this case study, various ways to partition a code between the microprocessor and FPGA are examine...
Reconfigurable computing offers the promise of performing computations in hardware to increase perfo...
Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable ha...
Sorting is perhaps the most widely studied problem in computer science and is frequently used as a b...
The execution speed of the FPGA processing elements are compared to the microprocessor processing el...
n the past few years, high-performance computing vendors have introduced many systems contain-ing bo...
For last few decades, reconfigurable devices have been extensively used in digital systems. Reconfig...
The combination of traditional microprocessors workstations and hardware-reconfigurable Field Progra...
Run-Time Reconfigured systems offer additional hardware resources to systems based on reconfigurable...
Summarization: Fine-grain reconfigurable devices suffer from the time needed to load the configurati...
Fine-grain reconfigurable devices suffer from the time needed to load the configuration bitstream. E...
Runtime reconfigurable systems built upon devices with partial reconfiguration can provide reduction...
The saturation of single-thread performance, along with the advent of the power wall, has resulted i...
Reconfigurable Computers (RC) can provide significant performance improvement for domain application...
FPGA based systems have been heavily used to prototype and test Application Specic Integrated Cir...
In this case study, various ways to partition a code between the microprocessor and FPGA are examine...