Performance and Analysis of Sorting Algorithms on the SRC 6 Reconfigurable Computer

Sorting is perhaps the most widely studied problem in computer science and is frequently used as a benchmark of a system’s performance. This work compares the execution speed of the FPGA processing elements to the microprocessor processing elements in the SRC 6 reconfigurable computer using the following algorithms for sorting unsigned integer keys: Quick Sort, Heap Sort, Radix Sort, Bitonic Sort, and Odd/Even Merge. SRC compiler performance is also examined. The results show that, for sorting, FPGA technology may not be the best processor choice and that factors such as memory bandwidth, clock speed, algorithm computational requirements and an algorithm’s ability to be pipelined all have an impact on FPGA performance. Keywords: reconfigurable computer, sorting, FPGA