An Evaluation of Intel’s Restricted Transactional Memory for CPAs

Abstract. With the release of their latest processor microarchitecture, codenamed Haswell, Intel added new Transactional Synchronization Extensions (TSX) to their processors ’ instruction set. These extensions include support for Restricted Transac-tional Memory (RTM), a programming model in which arbitrary sized units of mem-ory can be read and written in an atomic manner. This paper describes the low-level RTM programming model, benchmarks the performance of its instructions and spec-ulates on how it may be used to implement and enhance Communicating Process Ar-chitectures