Abstract-Fault-tolerant approaches have been widcly em ployed to improve the yield of ULSI and WSI processor arrays. In this paper, we propose a host-driven reconfiguration scheme, called HEX-REPAIR, for hexagonal processor arrays charac terized by a large number of relatively simple cells. Such arrays have heen shown to be the most efficient for many digital signal processing applications, such as matrix multiplication, and for some classes of filtering operations. Reconfiguration for these arrays is made difficult by the asymmetric nature of the inter connection network and the need for keeping the switching overheads at a minimum. The algorithm presented in this pa per meets these requirements. In addition, it has excellent fault coverag...
Part 3: Session 3: Parallel ArchitecturesInternational audienceIn a multiprocessor array, some proce...
A fault-tolerant array for matrix multiplication that explicitly incorporates mechanisms for easy te...
The problem of reconfiguring two-dimensional VLSI arrays with faults is to find a maximum logical ar...
In large VLSI/WSI arrays, improved reliability and yield can be obtained through reconfiguration tec...
Abstract—This paper proposes an efficient techniques to reconfigure a two-dimensional degradable ver...
The rapid advancement in VLSI technology is making it feasible to consider the construction of a par...
AbstractAn approach to design fault-tolerant hexagonal systolic array (SA) for multiplication of rec...
With few exceptions, the two issues of algorithm design and fault tolerance for processor arrays hav...
This thesis addresses the problem of constructing a flawless subarray from a defective VLSI/WSI arra...
This paper deals with efficient methods for mapping arbitrary parallel algorithms onto faulty genera...
In this paper we consider the problem of reconfiguring processor arrays subject to computational loa...
This thesis examines three specific issues of defect-tolerant VLSI: (1) design and reconfiguration o...
Vita.This dissertation present new approaches for testing and reconfiguring several types of wafer-s...
Wafer-scale integration (WSI) is a design technique that enables _ntegrated circuits to be designed ...
This paper proposes an efficient techniques to reconfigure a two-dimensional degradable very large s...
Part 3: Session 3: Parallel ArchitecturesInternational audienceIn a multiprocessor array, some proce...
A fault-tolerant array for matrix multiplication that explicitly incorporates mechanisms for easy te...
The problem of reconfiguring two-dimensional VLSI arrays with faults is to find a maximum logical ar...
In large VLSI/WSI arrays, improved reliability and yield can be obtained through reconfiguration tec...
Abstract—This paper proposes an efficient techniques to reconfigure a two-dimensional degradable ver...
The rapid advancement in VLSI technology is making it feasible to consider the construction of a par...
AbstractAn approach to design fault-tolerant hexagonal systolic array (SA) for multiplication of rec...
With few exceptions, the two issues of algorithm design and fault tolerance for processor arrays hav...
This thesis addresses the problem of constructing a flawless subarray from a defective VLSI/WSI arra...
This paper deals with efficient methods for mapping arbitrary parallel algorithms onto faulty genera...
In this paper we consider the problem of reconfiguring processor arrays subject to computational loa...
This thesis examines three specific issues of defect-tolerant VLSI: (1) design and reconfiguration o...
Vita.This dissertation present new approaches for testing and reconfiguring several types of wafer-s...
Wafer-scale integration (WSI) is a design technique that enables _ntegrated circuits to be designed ...
This paper proposes an efficient techniques to reconfigure a two-dimensional degradable very large s...
Part 3: Session 3: Parallel ArchitecturesInternational audienceIn a multiprocessor array, some proce...
A fault-tolerant array for matrix multiplication that explicitly incorporates mechanisms for easy te...
The problem of reconfiguring two-dimensional VLSI arrays with faults is to find a maximum logical ar...