Equivalence Checking for Compiler Transformations in Behavioral Synthesis

Abstract—Behavioral synthesis entails application of a se-quence of transformations to compile a high-level description of a hardware design (e.g., in C/C++/SystemC) into a Register-Transfer Level (RTL) implementation. We present a scalable equivalence checking framework to validate the correctness of compiler transformations employed by behavioral synthesis. Our approach is based on dual-rail symbolic simulation of the input and output design representations of a transformation. We have evaluated our framework on transformations applied to several designs by an open source behavioral synthesis tool, and we present initial results demonstrating the approach. Keywords—Equivalence checking, behavioral synthesis, trans-formation. I