OU-chip main memory has long been a bottleneck for system per-formance. With increasing memory pressure due to multiple on-chip cores, eUective cache utilization is important. In a system with limited cache space, we would ideally like to prevent 1) cache pol-lution, i.e., blocks with low reuse evicting blocks with high reuse from the cache, and 2) cache thrashing, i.e., blocks with high reuse evicting each other from the cache. In this paper, we propose a new, simple mechanism to predict the reuse behavior of missed cache blocks in a manner that mitigates both pollution and thrashing. Our mechanism tracks the addresses of recently evicted blocks in a structure called the Evicted-Address Filter (EAF). Missed blocks whose addresses are prese...
As CPU data requests to the level-one (L1) data cache (DC) can represent as much as 25% of an embedd...
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay...
Blocking is a well-known optimization technique for improving the effectiveness of memory hierarchie...
Efficient cache hierarchy management is of a paramount importance when designing high performance pr...
We introduce a novel approach to predict whether a block should be allocated in the cache or not upo...
We introduce a set of new Compression-Aware Management Policies (CAMP) for on-chip caches that emplo...
<p>We introduce a set of new Compression-Aware Management Policies (CAMP) for on-chip caches that em...
Caches mitigate the long memory latency that limits the performance of modern processors. However, c...
In this paper, we propose a new block selection policy for Last-Level Caches (LLCs) that decides, ba...
Last-level caches bridge the speed gap between processors and the off-chip memory hierarchy and redu...
Last-level caches (LLCs) bridge the processor/memory speed gap and reduce energy consumed per access...
As data prefetching is used in embedded processors, it is crucial to reduce the wasted energy for im...
Cache misses are currently a major factor in the cost of garbage collection, and we expect them to d...
As CPU data requests to the level-one (L1) data cache (DC) can represent as much as 25 % of an embed...
Low-latency data access is essential for performance. To achieve this, processors use fast first-lev...
As CPU data requests to the level-one (L1) data cache (DC) can represent as much as 25% of an embedd...
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay...
Blocking is a well-known optimization technique for improving the effectiveness of memory hierarchie...
Efficient cache hierarchy management is of a paramount importance when designing high performance pr...
We introduce a novel approach to predict whether a block should be allocated in the cache or not upo...
We introduce a set of new Compression-Aware Management Policies (CAMP) for on-chip caches that emplo...
<p>We introduce a set of new Compression-Aware Management Policies (CAMP) for on-chip caches that em...
Caches mitigate the long memory latency that limits the performance of modern processors. However, c...
In this paper, we propose a new block selection policy for Last-Level Caches (LLCs) that decides, ba...
Last-level caches bridge the speed gap between processors and the off-chip memory hierarchy and redu...
Last-level caches (LLCs) bridge the processor/memory speed gap and reduce energy consumed per access...
As data prefetching is used in embedded processors, it is crucial to reduce the wasted energy for im...
Cache misses are currently a major factor in the cost of garbage collection, and we expect them to d...
As CPU data requests to the level-one (L1) data cache (DC) can represent as much as 25 % of an embed...
Low-latency data access is essential for performance. To achieve this, processors use fast first-lev...
As CPU data requests to the level-one (L1) data cache (DC) can represent as much as 25% of an embedd...
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay...
Blocking is a well-known optimization technique for improving the effectiveness of memory hierarchie...