We introduce a novel approach to predict whether a block should be allocated in the cache or not upon a miss based on past reuse behavior during its lifetime in the cache. It introduces a new reuse model that makes a single-entry bypass buffer suffice to exploit the spatial locality in non-allocated blocks. It also applies classical two-level branch prediction to the reuse history patterns to predict whether the block should be allocated or not. Our evaluation of the scheme, based on five benchmarks from SPEC'95 and a set of six multimedia and database applications, shows that the prediction accuracy is between 66 and 94% across the applications and can result in a miss rate reduction of between 1 and 32% with an average of 12% (using the ...
Last-Level Cache (LLC) represents the bulk of a modern CPU processor's transistor budget and is esse...
OU-chip main memory has long been a bottleneck for system per-formance. With increasing memory press...
Worst-case execution time (WCET) analysis of systems with data caches is one of the key challenges i...
We introduce a novel approach to predict whether a block should be allocated in the cache or not upo...
We develop a reuse distance/stack distance based analytical modeling framework for efficient, online...
In this paper, we propose a new block selection policy for Last-Level Caches (LLCs) that decides, ba...
Cache replacement and branch prediction are two important microarchitectural prediction techniques f...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
Block memory operations are frequently performed by the operating system and consume an increasing f...
Feedback-directed optimization has become an increasingly impor-tant tool in designing and building ...
The increasing speed gap between processor microarchitectures and memory technologies can potentiall...
As buffer cache is used to overcome the speed gap between processor and storage devices, performance...
Energy is an increasingly important consideration in memory system design. Although caches can save ...
Efficient cache hierarchy management is of a paramount importance when designing high performance pr...
Feedback-directed optimization has become an increasingly important tool in designing and building o...
Last-Level Cache (LLC) represents the bulk of a modern CPU processor's transistor budget and is esse...
OU-chip main memory has long been a bottleneck for system per-formance. With increasing memory press...
Worst-case execution time (WCET) analysis of systems with data caches is one of the key challenges i...
We introduce a novel approach to predict whether a block should be allocated in the cache or not upo...
We develop a reuse distance/stack distance based analytical modeling framework for efficient, online...
In this paper, we propose a new block selection policy for Last-Level Caches (LLCs) that decides, ba...
Cache replacement and branch prediction are two important microarchitectural prediction techniques f...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
Block memory operations are frequently performed by the operating system and consume an increasing f...
Feedback-directed optimization has become an increasingly impor-tant tool in designing and building ...
The increasing speed gap between processor microarchitectures and memory technologies can potentiall...
As buffer cache is used to overcome the speed gap between processor and storage devices, performance...
Energy is an increasingly important consideration in memory system design. Although caches can save ...
Efficient cache hierarchy management is of a paramount importance when designing high performance pr...
Feedback-directed optimization has become an increasingly important tool in designing and building o...
Last-Level Cache (LLC) represents the bulk of a modern CPU processor's transistor budget and is esse...
OU-chip main memory has long been a bottleneck for system per-formance. With increasing memory press...
Worst-case execution time (WCET) analysis of systems with data caches is one of the key challenges i...