In this work, we investigate the problem of automatically mapping applications onto a coarse-grained reconfigurable architecture and propose an efficient algorithm to solve the problem. We formalize the mapping problem and show that it is NP-complete. To solve the problem within a reasonable amount of time, we divide it into three subproblems: covering, partitioning and layout. Our empirical results demonstrate that our technique produces nearly as good performance as hand-optimized outputs for many kernels. 1. Introduction an
This paper introduces a method which can be used to map applications written in a high level source ...
We propose that, in order to meet high computational demands, the application development has to be ...
In this paper we study the performance improvements and trade-offs derived from an optimized mapping...
Abstract: It is widely known that bandwidth limitations degrade parallel systems ’ performance. This...
This paper presents a compiler methodology for memory-aware mapping on 2-Dimensional coarse-grained ...
With the increasing demand for flexible yet highly efficient archi-tecture platforms for media appli...
Today the most commonly used system architectures in data processing can be divided into three categ...
ABSTRACT The increasing requirements for more flexibility and higher performance have drawn attentio...
In this paper, the problem of spatial mapping is defined. Reasons are presented to show why performi...
Coarse-Grained Reconfigurable Architectures (CGRAs) are programmable logic devices with large coarse...
Coarse-grained reconfigurable arrays (CGRAs) are a very promising platform, providing both up to 10-...
Abstract — Recently coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attent...
Coarse-grain reconfigurable architectures consist of a large number of processing elements (PEs) con...
Coarse-Grained Reconfigurable Arrays (CGRAs) are a very promising platform, providing both, up to 10...
Coarse-Grained Reconfigurable Architecture (CGRA) is a very promising platform that provides fast tu...
This paper introduces a method which can be used to map applications written in a high level source ...
We propose that, in order to meet high computational demands, the application development has to be ...
In this paper we study the performance improvements and trade-offs derived from an optimized mapping...
Abstract: It is widely known that bandwidth limitations degrade parallel systems ’ performance. This...
This paper presents a compiler methodology for memory-aware mapping on 2-Dimensional coarse-grained ...
With the increasing demand for flexible yet highly efficient archi-tecture platforms for media appli...
Today the most commonly used system architectures in data processing can be divided into three categ...
ABSTRACT The increasing requirements for more flexibility and higher performance have drawn attentio...
In this paper, the problem of spatial mapping is defined. Reasons are presented to show why performi...
Coarse-Grained Reconfigurable Architectures (CGRAs) are programmable logic devices with large coarse...
Coarse-grained reconfigurable arrays (CGRAs) are a very promising platform, providing both up to 10-...
Abstract — Recently coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attent...
Coarse-grain reconfigurable architectures consist of a large number of processing elements (PEs) con...
Coarse-Grained Reconfigurable Arrays (CGRAs) are a very promising platform, providing both, up to 10...
Coarse-Grained Reconfigurable Architecture (CGRA) is a very promising platform that provides fast tu...
This paper introduces a method which can be used to map applications written in a high level source ...
We propose that, in order to meet high computational demands, the application development has to be ...
In this paper we study the performance improvements and trade-offs derived from an optimized mapping...