An algorithm for mapping loops onto coarse-grained reconfigurable architectures

With the increasing demand for flexible yet highly efficient archi-tecture platforms for media applications, there is a growing interest in the Coarse-grained Reconfigurable Architectures (CRAs). While many CRAs have demonstrated impressive performance improve-ment, the lack of compilation technology for such architectures causes a bottleneck in the current design process. In this paper, we present a novel mapping algorithm designed to support Recon-figurable ALU Array (RAA) architectures, that represent a signifi-cant class of CRAs. More specifically we present a core mapping algorithm that addresses the problem of placing and routing the op-erations of a loop body onto the ALU array, to be executed in a loop pipelined fashion. Experimental results using our mapping al-gorithm on a typical RAA show that our algorithm not only has very fast compilation time but can also generate quality mappings exhibiting high memory bandwidth utilization and low global inter-connection requirements. Comparison with manual mapping also indicates that our algorithm can generate near-optimal mappings for several loops