Investigating average versus worst-case timing behavior of data caches and data scratchpads

This paper shows that a program using a time-predictable memory system for data storage can achieve a similar worst-case execution time (WCET) to the average-case execution time (ACET) using a conventional heuristic-based memory system including a data cache. This result is useful within any embedded system where time-predictability and performance are both important, particularly hard real-time systems carrying out intensive data processing activities. It is a counter-example to the conventional wisdom that time-predictable means “slow” in comparison to ACET-focused heuristics. To carry out the investigation, 36 “memory access mod-els ” are derived from benchmark programs and assumed to be representative of typical code. The models gener-ate LOAD/STORE instructions to exercise a data cache or scratchpad memory management unit (SMMU). The ACET is determined for the data cache and the WCET is deter-mined for the SMMU. After improvements are applied, re-sults show that the SMMU WCET is within 5 % of the data cache ACET for 34 models. In 16 of 36 cases, the SMMU WCET is better than the data cache ACET.