Scratchpads have been widely proposed as an alternative to caches for embedded systems. Advantages of scratchpads in-clude reduced energy consumption in comparison to a cache and access latencies that are independent of the preceding memory access pattern. The latter property makes memory accesses time-predictable, which is useful for hard real-time tasks as the worst-case execution time (WCET) must be safely estimated in order to check that the system will meet timing requirements. However, data must be explicitly moved between scratch-pad and external memory as a task executes in order to make best use of the limited scratchpad space. When dy-namic data is moved, issues such as pointer aliasing and pointer invalidation become problematic....
Abstract—A method to both reduce energy and improve perfor-mance in a processor-based embedded syste...
In modern processor architectures, caches are widely used to shorten the gap between the processor s...
Abstract—This paper compares two proposed alternatives to conventional instruction caches: a scratch...
This report proposes the scratchpad memory management unit (SMMU) to act as a perfect data cache for...
This paper shows that a program using a time-predictable memory system for data storage can achieve ...
Safety-critical embedded systems having to meet real-time constraints are expected to be highly pred...
Safety-critical embedded systems having to meet real-time con-straints are to be highly predictable ...
Safety-critical embedded systems having to meet real-time con-straints are expected to be highly pre...
Scratchpad memory has been introduced as a replacement for cache memory as it improves the performan...
Hard real-time tasks must meet their deadline in all situations, including in the worst-case one, ot...
In this research we propose a highly predictable, low overhead and yet dynamic, memory allocation st...
Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the dif...
Abstract—Hardware-managed caches introduce large amounts of timing variability, complicating real-ti...
In this paper, we propose a methodology for energy reduction and performance improvement. The target...
Abstract—We propose a code scratchpad memory (SPM) management technique with demand paging for embed...
Abstract—A method to both reduce energy and improve perfor-mance in a processor-based embedded syste...
In modern processor architectures, caches are widely used to shorten the gap between the processor s...
Abstract—This paper compares two proposed alternatives to conventional instruction caches: a scratch...
This report proposes the scratchpad memory management unit (SMMU) to act as a perfect data cache for...
This paper shows that a program using a time-predictable memory system for data storage can achieve ...
Safety-critical embedded systems having to meet real-time constraints are expected to be highly pred...
Safety-critical embedded systems having to meet real-time con-straints are to be highly predictable ...
Safety-critical embedded systems having to meet real-time con-straints are expected to be highly pre...
Scratchpad memory has been introduced as a replacement for cache memory as it improves the performan...
Hard real-time tasks must meet their deadline in all situations, including in the worst-case one, ot...
In this research we propose a highly predictable, low overhead and yet dynamic, memory allocation st...
Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the dif...
Abstract—Hardware-managed caches introduce large amounts of timing variability, complicating real-ti...
In this paper, we propose a methodology for energy reduction and performance improvement. The target...
Abstract—We propose a code scratchpad memory (SPM) management technique with demand paging for embed...
Abstract—A method to both reduce energy and improve perfor-mance in a processor-based embedded syste...
In modern processor architectures, caches are widely used to shorten the gap between the processor s...
Abstract—This paper compares two proposed alternatives to conventional instruction caches: a scratch...