Instruction scheduling for dynamic hardware configurations

Although the huge reconfiguration latency of the avail-able FPGA platforms is a well-known shortcoming of the current FCCMs, little research in instruction scheduling has been undertaken to eliminate or diminish its negative influence on performance. In this paper, we introduce an instruction scheduling algorithm that minimizes the num-ber of executed hardware reconfiguration instructions tak-ing into account the ”FPGA area placement conflicts ” be-tween the available configurations. The algorithm is based on compiler analyses and feedback-directed techniques and it can switch from hardware execution to software execution for an operation, when the reconfiguration latency could not be reduced. The algorithm has been tested for the M-JPEG encoder application and the real hardware implementations for DCT, Quantization and VLC operations. Based on sim-ulation results, we determine that, while a simple schedul-ing produces a significant performance decrease, our pro-posed scheduling contributes for up to 16x M-JPEG en-coder speedup. 1