Instruction Set and Functional Unit Synthesis for SIMD Processor Cores

Abstract—This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algo-rithm. Given an initial assembly code and a timing constraint, the proposed algorithm synthesizes an area-optimized processor core with optimal SIMD functional units. It also synthesizes a SIMD instruction set. The input initial assembly code is assumed to run on a full-resource SIMD processor (virtual processor) which has all the possible SIMD functional units. In our algorithm, we in-troduce the SIMD operation decomposition and apply it to the initial assembly code and the full-resource SIMD processor. By gradually reducing SIMD operations or decomposing SIMD oper-ations, we can finally find a processor core with small area under the given timing constraint. The promising experimental results are also shown. I