Application Specific Instruction-set Processor Using a Parametrizable multi-SIMD Synthesizeable Model Supporting Design Space Exploration

In this thesis, we provide a synthesizable model for supporting design space exploration of application-specific instruction-set processors. The model is written in a high-level of abstraction hardware description language Bluespec System Verilog and is parametrized to support different configurations for use in the design space exploration. To test the model, different applications from the media domain was selected to run on some of the configurations from the design space exploration. The applications were also run on a standard general processor for comparison. The results show that there is a performance gain compared to the standard processor, but with a higher cost of resources. With the utilization of the resources the scheduling of the applications turned out to be critical for this performance gain. The synthesizable model also shows that there is a consideration of the maximum clock frequency and memory constraints that the theoretical design space exploration model does not take into account