A Task-Level Hierarchical Memory Model for System Synthesis of Multiprocessors

Abstract This paper introduces the first high-level (task-level) model of hierarchical memories and describes a scheduling and allocation algorithm for system-level synthesis of heterogeneous multiprocessors. Caches are essential for modern RISC embedded cores to obtain sustained high performance. However, caches have received limited use in priority-driven preemptive real-time sys-tems due to the unpredictability of caches—average-case improve-ments are of no use in systems with hard deadlines. Program-level cache models do not take into account preemptions between mul-tiple tasks running at multiple rates on embedded cores. Our task-level model of performance in the presence of memory hierarchies provides an efficient means to bound the guaranteed memory per-formance of tasks running in a multi-rate, multi-tasking environ-ment. Our system synthesis algorithm uses software-based cache partitioning and reservation techniques to guarantee cache hits for some tasks and therefore improve task schedulability. Experi-mental results show that our model significantly improves schedu-lability of real-time tasks and can be evaluated efficiently during system-level synthesis.