Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way the system is not compositional so the overall performance is difficult to predict and the integration of new tasks expensive. This paper proposes a new method that imposes compositionality to the system’s performance and makes different memory hierarchy optimizations possible for multimedia communicating tasks when running on embedded multiprocessor architectures. The method is based on a cache allocation strategy that assigns sets of the unified cache exclusively to tasks and to the communication buffers. We also analytically formulate the problem and describe a metho...
This study proposes a technique which leverages data cache reconfigura-bility to address the problem...
Since different companies are introducing new capabilities and features on their products, the dema...
The evolution of microprocessor design in the last few decades has changed significantly, moving fro...
The paper presents a task allocation scheme for system-level synthesis of multirate real-time tasks ...
This research aims to explore possible solutions to improvementof performance in multimedia processo...
Embedded systems are getting popular in today’s world. They are usually small and thus have a limite...
Memory (cache, DRAM, and disk) is in charge of providing data and instructions to a computer\u27s pr...
This paper presents CaM, a holistic cache and memory bandwidth resource allocation strategy for mult...
The paper explores cache strategies for multimedia. Although many architectural improvements have be...
In the world of complex SoCs for consumer applica-tions, multiprocessor architectures usually deploy...
This work is based on our philosophy of providing inter-layer system-level power awareness in comput...
Click on the DOI link to access the article (may not be free).High processing speed is required to s...
This study proposes a technique which leverages data cache reconfigurability to address the problem ...
Abstract—Power consumption is an important design issue of current multimedia embedded systems. Data...
Abstract This paper introduces the first high-level (task-level) model of hierarchical memories and ...
This study proposes a technique which leverages data cache reconfigura-bility to address the problem...
Since different companies are introducing new capabilities and features on their products, the dema...
The evolution of microprocessor design in the last few decades has changed significantly, moving fro...
The paper presents a task allocation scheme for system-level synthesis of multirate real-time tasks ...
This research aims to explore possible solutions to improvementof performance in multimedia processo...
Embedded systems are getting popular in today’s world. They are usually small and thus have a limite...
Memory (cache, DRAM, and disk) is in charge of providing data and instructions to a computer\u27s pr...
This paper presents CaM, a holistic cache and memory bandwidth resource allocation strategy for mult...
The paper explores cache strategies for multimedia. Although many architectural improvements have be...
In the world of complex SoCs for consumer applica-tions, multiprocessor architectures usually deploy...
This work is based on our philosophy of providing inter-layer system-level power awareness in comput...
Click on the DOI link to access the article (may not be free).High processing speed is required to s...
This study proposes a technique which leverages data cache reconfigurability to address the problem ...
Abstract—Power consumption is an important design issue of current multimedia embedded systems. Data...
Abstract This paper introduces the first high-level (task-level) model of hierarchical memories and ...
This study proposes a technique which leverages data cache reconfigura-bility to address the problem...
Since different companies are introducing new capabilities and features on their products, the dema...
The evolution of microprocessor design in the last few decades has changed significantly, moving fro...