Technology-organization tradeoffs in the architecture of a high-performance processor.

To design computers which reach the performance limits of the implementation technology, one must understand the relationships between the technology and organization of the processor. This thesis presents a multilevel performance optimization methodology to analyze these relationships. All technology-organization relationships can be analyzed as tradeoffs between CPU cycle time ($t\sb{\rm CPU}$) and CPU cycles per instruction (CPI), the product of which, time per instruction (TPI), is used as the performance metric in this thesis. Two new analysis tools: (1) a timing analyzer for $t\sb{\rm CPU}$ and (2) a trace-driven cache simulator for CPI are an integral part of the optimization methodology. The methodology is extensively validated using a high performance processor design that is implemented out of gallium arsenide chips and multichip module packaging. The results of this validation are a number of general guidelines for high performance processor design. The methodology is first applied to the design of the first-level cache of a two-level cache hierarchy. Simple expressions are derived that provide the access time of on-chip and MCM based caches of various sizes. The access time of the first-level cache is on the critical path of the processor and so determines $t\sb{\rm CPU}$. When the first-level cache is unpiplined maximum performance is reached with small caches that have short access times. When the first-level cache is pipelined higher maximum performance is reached with larger caches that have longer access times. This is possible because the increase in CPI, that pipelining has the potential to create, can be effectively hidden by using static scheduling techniques. Applying the methodology to other parts of the cache-hierarchy produces the following results. Second-level caches that are split between instructions and data have performance and implementation benefits. The choice of write-policy (write-back or write-through) depends on the effective access time of the next higher level of the memory hierarchy. Adding concurrency to the cache-hierarchy in the form of write-buffering of the second-level cache or a non-blocking first-level cache provides modes reductions in CPI. When the reduction in CPI is weighed against the increased implementation complexity and possible increase in $t\sb{\rm CPU}$ these techniques for improving performance are not nearly as effective as increasing the sizes of the caches and pipelining the first-level cache.Ph.D.Applied SciencesComputer scienceElectrical engineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/128829/2/9208618.pd