Raising the abstraction level of RTL design

The register transfer abstraction (RTL) has been estab-lished as the industrial standard for ASIC design, soft IP ex-change and the backend interface for chip design at higher level. Unfortunately, the “synthesizable ” VHDL/Verilog in-carnation of the RTL abstraction has problems which pre-vent it from more productive use. For example, the confu-sion as the result of using simulation semantics for synthe-sis purpose, the lack of facility for component reuse at the “protocol ” level, and the lack of memory abstraction. Af-ter a detailed discussion of these problems, this paper pro-poses a new RTL abstraction, called MetaRTL, which can be implemented by a modest extension to the traditional im-perative programming languages. The productivity gain is further demonstrated by the description of a synthesis tool, called MetaSyn, which provides the “added-value”. Exper-iments on the benchmark set show that MetaRTL is far more concise than the “synthesizable ” HDL specification, and in-curs no overhead for synthesis result.