Modern SoCs gain a high level of parallelism by using both general purpose processors and a number of data processing entities (DPE), dedicated to certain heavy functionalities. As a consequence, most systems devote DPEs to executing functions with high performance rather than using dedicated hardware. Reusing already existing and pre-verified IPs through abstraction methodologies is a key idea to meet time-to-market requirements and to reduce the error risk. Rough abstraction techniques lead to non efficient software code, that results in being very limited by hardware communication protocols and data types. This paper proposes an abstraction methodology that produces optimized code. Protocol refinement and data redefinitions are exploited...
International audienceThe growing requirement on the correct design of a high performance DSP system...
Transaction-level modeling (TLM) is the most promising technique to deal with the increasing complex...
International audienceIn this paper, we propose an efficient IP block based design environment for h...
High performance provided by multi-processor System-on-Chips (MPSoCs) often induces designers to cho...
With the advent of heterogeneous multi-processor system-on-chips (MPSoCs), hardware/software partiti...
The register transfer abstraction (RTL) has been estab-lished as the industrial standard for ASIC de...
IP-reuse allows designers to exploit already imple-mented and verified RTL IP cores while concentrat...
The arising complexity of modern system-on-chips (SoCs) makes the reuse of existent IP cores a key s...
Plugging an IP core into an embedded platform implies the generation of a device driver complying wi...
International audienceDue to increasing complexity of SoC and shortening life time cycle of product,...
The paper presents a novel abstraction methodology for generating time-and power-annotated TLM model...
Embedded network software has become increasingly interesting for both researchand business as more ...
We present a method to automatically generate a synthesizable C++specification from the given RTL de...
IP core integration into an embedded platform implies the implementation of a customized device driv...
Abstract. System-on-Chip (SoC) design raises an abstraction level in hardware (HW) design beyond a d...
International audienceThe growing requirement on the correct design of a high performance DSP system...
Transaction-level modeling (TLM) is the most promising technique to deal with the increasing complex...
International audienceIn this paper, we propose an efficient IP block based design environment for h...
High performance provided by multi-processor System-on-Chips (MPSoCs) often induces designers to cho...
With the advent of heterogeneous multi-processor system-on-chips (MPSoCs), hardware/software partiti...
The register transfer abstraction (RTL) has been estab-lished as the industrial standard for ASIC de...
IP-reuse allows designers to exploit already imple-mented and verified RTL IP cores while concentrat...
The arising complexity of modern system-on-chips (SoCs) makes the reuse of existent IP cores a key s...
Plugging an IP core into an embedded platform implies the generation of a device driver complying wi...
International audienceDue to increasing complexity of SoC and shortening life time cycle of product,...
The paper presents a novel abstraction methodology for generating time-and power-annotated TLM model...
Embedded network software has become increasingly interesting for both researchand business as more ...
We present a method to automatically generate a synthesizable C++specification from the given RTL de...
IP core integration into an embedded platform implies the implementation of a customized device driv...
Abstract. System-on-Chip (SoC) design raises an abstraction level in hardware (HW) design beyond a d...
International audienceThe growing requirement on the correct design of a high performance DSP system...
Transaction-level modeling (TLM) is the most promising technique to deal with the increasing complex...
International audienceIn this paper, we propose an efficient IP block based design environment for h...