Synthesizing SystemVerilog Busting the Myth that SystemVerilog is only for Verification

SystemVerilog is not just for Verification! When the SystemVerilog standard was first devised, one of the primary goals was to enable creating synthesizable models of complex hardware designs more accurately and with fewer lines of code. That goal was achieved, and Synopsys has done a great job of implementing SystemVerilog in both Design Compiler (DC) and Synplify-Pro. This paper examines in detail the synthesizable subset of SystemVerilog for ASIC and FPGA designs, and presents the advantages of using these constructs over traditional Verilog. Readers will take away from this paper new RTL modeling skills that will indeed enable modeling with fewer lines of code, while at the same time reducing potential design errors and achieving high synthesis Quality of Results (QoR). Target audience: Engineers involved in RTL design and synthesis, targeting ASIC and FPGA implementations. Note: The information in this paper is based on Synopsys Design Compiler (also called HDL Compiler) version 2012.06-SP4 and Synopsys Synplify-Pro version 2012.09-SP1. These were the most curren