Speculatively issued instructions may be particularly sensitive to increases in pipeline depth. Our results indicate that as pipeline depth increases, speculation increases the percentage of issue queue instructions that are waiting to be potentially re-issued in case of a mis-speculation. To compensate, issue queues are larger and thus more power hungry. We propose an alternative design called the Dual Issue Queue, that retains pre- and post-issue instruc-tions in separate, smaller queues, saving 18 % of issue queue power dissipation without degrading performance
Value speculation has been proposed as a technique that can overcome true data dependencies, hide me...
Control and data flow speculation can improve processor performance through increased ILP. First it ...
Large instruction windows and issue queues are key to exploiting greater instruction level paralleli...
In the modern era of wire-dominated architectures, specific effort must be made to reduce needless c...
In this paper, we propose a new issue queue design that is capable of scheduling reusable instructio...
A simultaneous multithreaded (SMT) processor is able to issue and execute instructions from several ...
The improved performance of current microprocessors brings with it increasingly complex and power-di...
In contemporary superscalar microprocessors, issue queue is a considerable energy dissipating compon...
Abstract. High-performance processors use data-speculation to reduce the execution time of programs....
As technology evolves, power density significantly increases and cooling systems become more complex...
In a dynamic reordering superscalar processor, the front-end fetches instructions and places them in...
International audienceTo maximize performance, out-of-order execution processors sometimes issue ins...
Simultaneous Multi-Threading (SMT) processors improve system performance by allowing concurrent exec...
Current trends in processor design are pointing to deeper and wider pipelines and superscalar archit...
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruc...
Value speculation has been proposed as a technique that can overcome true data dependencies, hide me...
Control and data flow speculation can improve processor performance through increased ILP. First it ...
Large instruction windows and issue queues are key to exploiting greater instruction level paralleli...
In the modern era of wire-dominated architectures, specific effort must be made to reduce needless c...
In this paper, we propose a new issue queue design that is capable of scheduling reusable instructio...
A simultaneous multithreaded (SMT) processor is able to issue and execute instructions from several ...
The improved performance of current microprocessors brings with it increasingly complex and power-di...
In contemporary superscalar microprocessors, issue queue is a considerable energy dissipating compon...
Abstract. High-performance processors use data-speculation to reduce the execution time of programs....
As technology evolves, power density significantly increases and cooling systems become more complex...
In a dynamic reordering superscalar processor, the front-end fetches instructions and places them in...
International audienceTo maximize performance, out-of-order execution processors sometimes issue ins...
Simultaneous Multi-Threading (SMT) processors improve system performance by allowing concurrent exec...
Current trends in processor design are pointing to deeper and wider pipelines and superscalar archit...
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruc...
Value speculation has been proposed as a technique that can overcome true data dependencies, hide me...
Control and data flow speculation can improve processor performance through increased ILP. First it ...
Large instruction windows and issue queues are key to exploiting greater instruction level paralleli...