A Software Transactional Memory System for an Asymmetric Processor Architecture

Due to the advent of multi-core processors and the con-sequent need for better concurrent programming abstrac-tions, new synchronization paradigms have emerged. A promising one, known as software transactional memory (STM), aims to use transactions as the key synchroniza-tion mechanism to ease program development as well as in-crease its performance. Many (if not all) of the current STM implementations target homogeneous architectures. In this paper we describe an implementation of an STM system for an asymmetric architecture, the Cell BE. We evaluated our Transactional Software Cache (TSC) mechanism using a well-known micro-benchmark (IntSet) and the Genome ap-plication from STAMP. The results show that an STM imple-mentation for the Cell architecture is feasible if the shared-memory programming model is adopted. When compared to a conventional lock-based implementation, the STM ver-sion of Genome obtained a performance gain of 84 % and 24 % with large and small input sets, respectively.