Software Transactional Memory Validation – Time and Space Considerations

With single thread performance hitting the power wall, hardware architects have turned to chip-level multiprocessing to increase pro-cessor performance. As a result, issues related to the construction of scalable and reliable multi-threaded applications have become increasingly important. One of the most pressing problems in con-current programming has been synchronizing accesses to shared data among multiple concurrent threads. Traditionally, accesses to shared memory have been synchro-nized using lock-based techniques resulting in scalability, compos-ability and safety problems. Recently, transactional memory has been shown to eliminate many problems associated with lock-based synchronization, and transactional constructs have been added to languages to facilitate programming with transactions. Therefore, providing an efficient software transactional memory (STM) im-plementation has been an important area of research. One of the largest overheads in an STM implementation is incurred in the val-idation procedure (that is, in ensuring correctness of transactional read operations). This paper presents novel solutions to reduce the validation overhead in an STM. We first present a validation algorithm that is linear in the in the number of read operations executed by a transaction, and yet does not add any overhead to transactional reads and writes. We then present an algorithm that uses bitmaps to encode information about transactional operations and further reduces both the time and space overheads related to validation. We evaluate the effectiveness of both algorithms in the context of a state-of-the-art STM implementation. 1