A Software Transactional Memory System For An Asymmetric Processor Architecture

Due to the advent of multi-core processors and the consequent need for better concurrent programming abstractions, new synchronization paradigms have emerged. A promising one, known as software transactional memory (STM), aims to use transactions as the key synchronization mechanism to ease program development as well as increase its performance. Many (if not all) of the current STM implementations target homogeneous architectures. In this paper we describe an implementation of an STM system for an asymmetric architecture, the Cell BE. We evaluated our Transactional Software Cache (TSC) mechanism using a well-known micro-benchmark (IntSet) and the Genome application from STAMP. The results show that an STM implementation for the Cell architecture is feasible if the shared-memory programming model is adopted. When compared to a conventional lock-based implementation, the STM version of Genome obtained a performance gain of 84% and 24% with large and small input sets, respectively. © 2008 IEEE.175182IBM SDK for multicore acceleration: Example library API reference, version 3.0, 2007Balart, J., Gonzalez, M., Martorell, X., Ayguade, E., Sura, Z., Chen, T., Zhang, T., O'brien, K., A novel asynchronous software cache implementation for the cell-be processor (2007) Proc. of the LCPC 07Cao Minh, C., Trautmann, M., Chung, J., McDonald, A., Bronson, N., Casper, J., Kozyrakis, C., Olukotun, K., An effective hybrid transactional memory system with strong isolation guarantees (2007) Proceedings of the 34th ISCADice, D., Shalev, O., Shavit, N., Transactional locking II (2006) Proceedings of the 20th DISCEichenberger, A.E., O'Brien, K., O'Brien, K., Wu, P., Chen, T., Oden, P.H., Prener, D.A., Gschwind, M., Optimizing compiler for the cell processor (2005) PACT '05: Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques, pp. 161-172Felber, P., Fetzer, C., Riegel, T., Dynamic performance tuning of word-based software transactional memory (2008) Proceedings of the 13th PPoPP, pp. 237-246Harris, T., Cristal, A., Unsal, O., Ayguade, E., Gagliardi, F., Smith, B., Valero, M., Transactional memory: An overview (2007) IEEE Micro, 27 (3), pp. 8-29Herlihy, M., Luchangco, V., Moir, M., Scherer, W., Software transactional memory for dynamic-sized data structures (2003) Twenty-Second Annual ACM SIGACT-SIGOPS PODCKahle, J.A., Day, M.N., Hofstee, H.P., Johns, C.R., Maeurer, T.R., Shippy, D., Introduction to the cell multiprocessor (2005) IBM J. Res. Dev, 49 (4-5), pp. 589-604Larus, J.R., Rajwar, R., (2007) Transactional Memory, , Morgan & Claypool PublishersMcDonald, A., Carlstrom, B.D., Chung, J., Minh, C.C., Chafi, H., Kozyrakis, C., Olukotun, K., Transactional memory: The hardware-software interface (2007) IEEE Micro, 27 (1), pp. 67-76O'Brien, K., O'Brie, K., Sura, Z., Chen, T., Zhang, T., Support OpenMP on Cell (2007) International Workshop on OpenMP (2007)Ohara, M., Inoue, H., Sohda, Y., Komatsu, H., Nakatani, T., MPI microtask for programming the Cell Broadband Engine processor (2006) IBM Systems Journal, 45 (1), pp. 85-102Sutter, H., Larus, J.R., Software and the concurrency revolution (2005) Queue, 3 (7), pp. 54-6