On Microprocessors, Memory Hierarchies, and Amdahl's Law

While preparing material for an article describing fundamental performance characteristics of Cray PVP and MPP architectures (O'Neal and Urbanic, 1997), it became apparent to us that a variation of Amdahl's Law could be written for any computing system featuring a memory hierarchy. Expressions for estimating cache efficiency and relative performance were developed first. We then were able to show how the same forms could be used to produce realistic bounds on system throughput. After formalizing the relationship between caching efficiency and relative performance, selected results are plotted and a basic analysis is performed. To fix ideas, a relevant application is demonstrated. Findings are summarized in closing