As algorithms scale to solve larger and larger MDPs, it becomes impossible to store all of the model information of the MDP and the supporting data structures of the algorithm in RAM. This motivates the study of the disk-based-cache efficiency of solution algorithms. We contrast the cache efficiency of normal value iteration with that of the P-EVA algorithm, and introduce the concept of “intrinsic cacheability.” We concentrate on prioritized solution methods, and demonstrate that the choice of priority metric greatly affects cache behavior. Experimental results indicate that the best priority metric allows problems which are four times larger than available RAM to be solved effectively
Abstract|As the performance gap between processors and main memory continues to widen, increasingly ...
While preparing material for an article describing fundamental performance characteristics of Cray P...
The ratio between processor speed and memory speed frequently makes efficient use of cache memory a ...
As algorithms scale to solve larger and larger MDPs, it be-comes impossible to store all of the mode...
We present a model that enables us to analyze the running time of an algorithm on a computer with a ...
) Sandeep Sen y Siddhartha Chatterjee z Submitted for publication Abstract We describe a model...
We study the impact of using different priority queues in the performance of Dijkstra’s SSSP algorit...
Blocking is a well-known optimization technique for improving the effectiveness of memory hierarchie...
Memory efficiency and locality have substantial impact on the performance of programs, particularly ...
The performance of value and policy iteration can be dramatically improved by eliminating redundant ...
In previous work, a cache-aware sparse matrix multiplication for linear programming interior point m...
As memory access times grow larger relative to processor cycle times, the cache performance of algor...
Obtaining high performance without machine-specific tuning is an important goal of scientific applic...
AbstractIn the present paper we describe and analyse a sieving algorithm for determining prime numbe...
This paper explores the relation between the structured parallelism exposed by the Decomposable BSP ...
Abstract|As the performance gap between processors and main memory continues to widen, increasingly ...
While preparing material for an article describing fundamental performance characteristics of Cray P...
The ratio between processor speed and memory speed frequently makes efficient use of cache memory a ...
As algorithms scale to solve larger and larger MDPs, it be-comes impossible to store all of the mode...
We present a model that enables us to analyze the running time of an algorithm on a computer with a ...
) Sandeep Sen y Siddhartha Chatterjee z Submitted for publication Abstract We describe a model...
We study the impact of using different priority queues in the performance of Dijkstra’s SSSP algorit...
Blocking is a well-known optimization technique for improving the effectiveness of memory hierarchie...
Memory efficiency and locality have substantial impact on the performance of programs, particularly ...
The performance of value and policy iteration can be dramatically improved by eliminating redundant ...
In previous work, a cache-aware sparse matrix multiplication for linear programming interior point m...
As memory access times grow larger relative to processor cycle times, the cache performance of algor...
Obtaining high performance without machine-specific tuning is an important goal of scientific applic...
AbstractIn the present paper we describe and analyse a sieving algorithm for determining prime numbe...
This paper explores the relation between the structured parallelism exposed by the Decomposable BSP ...
Abstract|As the performance gap between processors and main memory continues to widen, increasingly ...
While preparing material for an article describing fundamental performance characteristics of Cray P...
The ratio between processor speed and memory speed frequently makes efficient use of cache memory a ...