As an efficient representation of Extended Finite State Machines, Multiway Decision Graphs (MDG) are suitable for automatic hardware verification of Register Transfer Level (RTL) designs. However, in some cases, MDG-based verification suffers from the state explosion problem. Some of cases are caused by the standard order used by MDG to order cross-terms that have the same top-level function symbol. These terms usually label decision nodes and must be ordered. We call this kind of state explosion the standard term ordering problem. A solution based on function renaming and cross-term rewriting is proposed in this paper. Experimental results show that this solution can solve the problem completely and thus increase the range of circuits that...
In this paper we describe an approach to interface Abstract State Machines (ASM) with Multiway Decis...
Model checking the design of a software system can be supported by providing an interface from a hig...
In this paper, we present a formal hardware verification framework linking ASM with MDG. ASM (Abstra...
Abstract:- The complexity of digital hardware designs has increased substantially with new advanceme...
Integrating formal verification techniques into the hardware design process provides the means to ri...
AbstractMultiway decision graphs are a new class of decision graphs for representing abstract states...
Multiway Decision Graphs (MDGs) subsume Binary Decision Diagrams (BDDs) by representing formulae whi...
We present a framework for the formal verification of abstract state machine (ASM) designs using the...
Traditional OBDD-based methods of automated verification suffer from the drawback that they require ...
This thesis demonstrates the effectiveness of Multiway Decision Graphs (MDG) to carry out the formal...
Abstract Multiway Decision Graphs (MDGs) are a canonical representation of a subset of many-sorted f...
Symbolic model-checking tools encounter state-explosion problem when verifying designs with large da...
In this paper we present several techniques for modeling and formal verification of the Fairisle Asy...
We address the problem of obtaining good variable orderings for the BDD representation of a system o...
In this paper, we propose an embedding of the MDG input languages in HOL. The MDG (Multiway Decision...
In this paper we describe an approach to interface Abstract State Machines (ASM) with Multiway Decis...
Model checking the design of a software system can be supported by providing an interface from a hig...
In this paper, we present a formal hardware verification framework linking ASM with MDG. ASM (Abstra...
Abstract:- The complexity of digital hardware designs has increased substantially with new advanceme...
Integrating formal verification techniques into the hardware design process provides the means to ri...
AbstractMultiway decision graphs are a new class of decision graphs for representing abstract states...
Multiway Decision Graphs (MDGs) subsume Binary Decision Diagrams (BDDs) by representing formulae whi...
We present a framework for the formal verification of abstract state machine (ASM) designs using the...
Traditional OBDD-based methods of automated verification suffer from the drawback that they require ...
This thesis demonstrates the effectiveness of Multiway Decision Graphs (MDG) to carry out the formal...
Abstract Multiway Decision Graphs (MDGs) are a canonical representation of a subset of many-sorted f...
Symbolic model-checking tools encounter state-explosion problem when verifying designs with large da...
In this paper we present several techniques for modeling and formal verification of the Fairisle Asy...
We address the problem of obtaining good variable orderings for the BDD representation of a system o...
In this paper, we propose an embedding of the MDG input languages in HOL. The MDG (Multiway Decision...
In this paper we describe an approach to interface Abstract State Machines (ASM) with Multiway Decis...
Model checking the design of a software system can be supported by providing an interface from a hig...
In this paper, we present a formal hardware verification framework linking ASM with MDG. ASM (Abstra...