Multiway Decision Graphs (MDGs) subsume Binary Decision Diagrams (BDDs) by representing formulae which are suitable for first-order model checking able to handle large datapath circuits. In this paper, we propose a reduction approach to improve MDGs model checking. We use a reduction platform based on combining MDGs with the rewriting engine of the HOL theorem prover. The idea is to prune the transition relation of the design using pre-proved theorems and lemmas from the specification given at system level. Then, the actual proof of temporal MDG formulae will be achieved by the MDGs model checker
Abstract. In this paper, we describe a first-order linear time temporal logic (LTL) model checker ba...
Traditional OBDD-based methods of automated verification suffer from the drawback that they require ...
Nowadays, the formal verification of hardware is gaining a lot of importance in the design flow of m...
The increasing complexity of hardware systems requires more and more sophisticated methods of verifi...
In this paper, we propose an embedding of the MDG input languages in HOL. The MDG (Multiway Decision...
Abstract In this paper, we provide a necessary infrastructure to define an abstract state exploratio...
While model checking suffers from the state space explosion problem, theorem proving is quite tediou...
Abstract. In this paper, we provide all the necessary infrastructure to define a high level states e...
AbstractThe combination of state exploration approach (mainly model checking) and deductive reasonin...
Formal verification of digital systems is achieved, today, using one of two main approaches: states ...
Abstract Multiway Decision Graphs (MDGs) are a canonical representation of a subset of many-sorted f...
Integrating formal verification techniques into the hardware design process provides the means to ri...
With the ever increasing complexity of the design of digital systems and the size of the circuits in...
Model checking the design of a software system can be supported by providing an interface from a hig...
AbstractModel checking the design of a software system can be supported by providing an interface fr...
Abstract. In this paper, we describe a first-order linear time temporal logic (LTL) model checker ba...
Traditional OBDD-based methods of automated verification suffer from the drawback that they require ...
Nowadays, the formal verification of hardware is gaining a lot of importance in the design flow of m...
The increasing complexity of hardware systems requires more and more sophisticated methods of verifi...
In this paper, we propose an embedding of the MDG input languages in HOL. The MDG (Multiway Decision...
Abstract In this paper, we provide a necessary infrastructure to define an abstract state exploratio...
While model checking suffers from the state space explosion problem, theorem proving is quite tediou...
Abstract. In this paper, we provide all the necessary infrastructure to define a high level states e...
AbstractThe combination of state exploration approach (mainly model checking) and deductive reasonin...
Formal verification of digital systems is achieved, today, using one of two main approaches: states ...
Abstract Multiway Decision Graphs (MDGs) are a canonical representation of a subset of many-sorted f...
Integrating formal verification techniques into the hardware design process provides the means to ri...
With the ever increasing complexity of the design of digital systems and the size of the circuits in...
Model checking the design of a software system can be supported by providing an interface from a hig...
AbstractModel checking the design of a software system can be supported by providing an interface fr...
Abstract. In this paper, we describe a first-order linear time temporal logic (LTL) model checker ba...
Traditional OBDD-based methods of automated verification suffer from the drawback that they require ...
Nowadays, the formal verification of hardware is gaining a lot of importance in the design flow of m...