Minimization of Multiway Decision Graphs for RTL Verification by Stochastic Optimization

Abstract:- The complexity of digital hardware designs has increased substantially with new advancements in electronic designs. It is becoming increasingly difficult to verify their correctness. MDGs have been proved to be a very effective tool in automatic hardware verification of RTL designs. In this paper, a method of variable reordering for Multiway Decision Graphs (MDG) is discussed. We present an automatic dynamic variable ordering algorithm for MDGs to reduce the effects of the state explosion problem. By contrast to ROBDDs, in MDGs difficulties are created by the presence of first order terms. The method we present here merges the benefits of stochastic evolution and sifting. It will be utilized to minimize the MDG size throughout the verification procedure. The effectiveness of our method is demonstrated by the empirical results provided