tor table size is performed. Section 5 reviews other related Reducing Wire Delay Penalty through Value Prediction

clock cycle time. One of the proposed solutions to this problem is based on clustering. In a clustered microarchitecture some of the critical components are partitioned into simpler structures, and the impact of wire delays is reduced as far as signals are kept local within the clusters. In a clustered architec-ture, deciding which instructions are executed in each clus-ter becomes a key issue. We will refer to this task as code partitioning. A code partitioning scheme determines how the dynamic instruction stream is split among the different clusters. Data dependences among instructions in different partitions correspond to inter-cluster communications, caused by inter-cluster communications can be reduced by 18 % through a simple value prediction scheme when the steering logic is designed to take advantage of the value predictor. The rest of this paper is organized as follows. Section 2 presents the assumed clustered architecture. Section 3 presents the partitioning heuristic implemented by the steering logic, and its specific adaptations to take advan-tage of value prediction, and provides a performance eval-uation. In Section 4, a sensitivity analysis regarding com-munication latency, communication bandwidth and predic