A generic FPGA based associative processor I.Petrescu*. D.Popescu.**

Abstract: Field Programmable Gates Arrays (FPFA) enabled the advent of a new computing paradigm, based on direct hardware computational algorithms implementation. The availability of the adequate CAD platforms, together with powerful FPGA‟s hardware resources, facilitates experimentations with various computational structures. The paper presents a generic, FPGA based, associative computational structure, which may generate implementations of many different applications specific processors, viewed as standalone black boxes, with dedicated inputs and outputs, and able to execute some given simple or complex algorithms. The associative generic processor is parameterized as word-length and word-numbers and operates in a word-parallel/bit-serial mode. Architectural details of the multi-comparand/multi-respondent associative generic processor and its functions are also provided, as well as a number of real algorithm implementations: max, min, sort, select, etc. 1