The Development of an Operating System for Reconfigurable Computing

Field programmable gate arrays are a class of integrated circuit that enable logic functions and interconnects to be programmed in almost real time. They can implement fine grained parallel computing architectures and algorithms in hardware that were previously the domain of custom VLSI. Field programmable gate arrays have shown themselves useful at exploiting concurrency in a range of applications such as text searching, image processing and encryption. When coupled with a microprocessor, which is more suited to computation involving complex control flow and non time critical requirements, they form a potentially versatile platform commonly known as a Reconfigurable Computer. Reconfigurable computing applications have traditionally had the exclusive use of the field programmable gate array, primarily because the logic densities of the available devices have been relatively similar in size compared to the application. But with the modern FPGA expanding beyond 10 million system gates, and through the use of dynamic reconfiguration, it has become feasible for several applications to share a single high density device. However, developing applications that share a device is difficult as the current design flow assumes th