An FPGA Based Reconfigurable Coprocessor Board Utilizing a Mathematics of Arrays

Abstract-- Work in progress at the University of Mis-souri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel field programmable gate array (FPGA) based reconfigurable coprocessor board (the Chameleon Coprocessor) being used to evaluate hardware architec-tures for speedup of array computation algorithms. These algorithms are developed using a Mathematics of Arrays (MOA). They provide a means to generate ad-dresses for data transfers that require less data move-ment than more traditional algorithms. In this manner, the address generation algorithms are acting as an in-telligent data prefetching mechanism or special purpose cache controller. Software implementations have been used to provide speedups on the order of 100 % over classical methods to the solution of heat transfer equa-tions on a uniprocessor. We extend these methods to application designs for the Chameleon Coprocessor. 1