Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level paral-lelism directly to the hardware. EPIC techniques which enable the compiler to represent control speculation, data dependence spec-ulation, and predication have individually been shown to be very effective. However, these techniques have not been studied in com-bination with each other. This paper presents the IMPACT EPIC Architecture to address the issues involved in designing processors based on these EPIC concepts. In particular, we focus on new execution and recovery models in which microarchitectural sup-port for predicated execution is also used to enable efficient recov-ery from exceptions caused by speculativ...
One of the main performance bottlenecks of processors today is the discrepancy between processor and...
VLIW/EPIC (Very Large Instruction Word/Explicitly Parallel Instruction Computing) processors are inc...
New generation superscalar processors combine predication with large resources. A typical example is...
The performance of modern processors is increasingly de-pendent on their ability to execute multiple...
Value speculation has the potential of extending instruction level parallelism by breaking the barri...
The Explicitly Parallel Instruction Computing (EPIC) architecture has been put forth as a viable arc...
textVery Large Instruction Word (VLIW)/Explicitly Parallel Instruction Computing (EPIC) processors ...
Compiler-controlled speculative execution has been shown to be effective in increasing the available...
The major specific contributions are: (1) We introduce a new compiler analysis to identify the memor...
277 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1997.For many applications, specul...
Control and data flow speculation can improve processor performance through increased ILP. First it ...
300 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2005.As we look both to newer appl...
A superscalar processor supporting speculative ex-ecution requires an instruction fetch mechanism th...
This paper describes a customisable architecture and the associated tools for a prototype EPIC (Expl...
Superscalar processors, which execute basic blocks sequentially, cannot use much instruction level p...
One of the main performance bottlenecks of processors today is the discrepancy between processor and...
VLIW/EPIC (Very Large Instruction Word/Explicitly Parallel Instruction Computing) processors are inc...
New generation superscalar processors combine predication with large resources. A typical example is...
The performance of modern processors is increasingly de-pendent on their ability to execute multiple...
Value speculation has the potential of extending instruction level parallelism by breaking the barri...
The Explicitly Parallel Instruction Computing (EPIC) architecture has been put forth as a viable arc...
textVery Large Instruction Word (VLIW)/Explicitly Parallel Instruction Computing (EPIC) processors ...
Compiler-controlled speculative execution has been shown to be effective in increasing the available...
The major specific contributions are: (1) We introduce a new compiler analysis to identify the memor...
277 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1997.For many applications, specul...
Control and data flow speculation can improve processor performance through increased ILP. First it ...
300 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2005.As we look both to newer appl...
A superscalar processor supporting speculative ex-ecution requires an instruction fetch mechanism th...
This paper describes a customisable architecture and the associated tools for a prototype EPIC (Expl...
Superscalar processors, which execute basic blocks sequentially, cannot use much instruction level p...
One of the main performance bottlenecks of processors today is the discrepancy between processor and...
VLIW/EPIC (Very Large Instruction Word/Explicitly Parallel Instruction Computing) processors are inc...
New generation superscalar processors combine predication with large resources. A typical example is...