Value Speculation Mechanisms for EPIC Architectures

Value speculation has the potential of extending instruction level parallelism by breaking the barrier caused by chains of pure dependencies. To date, the literature has focused primarily on implicitly parallel architectures with superscalar cores. This paper presents a scheme for integrating value speculation into an explictly parallel instruction computer ISA, such as IA-64 or HPL-PD. It presents a novel approach to recovering from incorrect speculation via the CHECKPRED instruction semantics. This technique can be coupled with interrupt handling mechanisms or register renaming techniques. The total effect is to eliminate the need for the patchup code. In addition, the paper addresses the selection of operations to value speculate. Using an optimizing compiler of the authors ’ construction, the critical paths of the SPECint95 benchmarks are analyzed. The interesting and non-intuitive result is that, although slicing a dependence chain in half should yield the highest speedup due to overlapped execution, in practice it doesn’t. Results for the maximal speedup resulting from various operation selection alternatives show that the predictability of an operation is also an important criterion for selection. The paper closes with recommendations for compiler-guided value selection decisions in EPIC architectures. 1