SWIFT: software implemented fault tolerance

To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. However, these advances make processors more susceptible to transient faults that can affect correctness. While reliable systems typically employ hardware tech-niques to address soft-errors, software techniques can pro-vide a lower-cost and more flexible alternative. This paper presents a novel, software-only, transient-fault-detection technique, called SWIFT. SWIFT efficiently manages re-dundancy by reclaiming unused instruction-level resources present during the execution of most programs. SWIFT also provides a high level of protection and performance with an enhanced control-flow checking mechanism. We evaluate an implementation of SWIFT on an Itanium 2 which demon-strates exceptional fault coverage with a reasonable perfor-mance cost. Compared to the best known single-threaded approach utilizing an ECC memory system, SWIFT demon-strates a 51 % average speedup.