A Parallel Rendering Algorithm for MIMD Architectures

Applications such as animation and scientific visualization demand high performance ren-dering of complex three dimensional scenes. To deliver the necessary rendering rates, highly parallel hardware architerfures are required. The challenge is then to design algorithms and software which effectively use the hardware parallelism. This paper describes a rendering al-gorithm targeted to distributed memory MIMD architectures. For maximum performance, the algorithm exploits both object-level and pixel-level parallelism. The behavior of the algorithm is examined both analytically z.nd experimentally. Its performance for large numbers of processors is found to be limited primarily by communication overheads. An experimental implementation for the Intel iPSC/860 shows increasing performance from 1 to 128 processors across a wide range of scene complexities. It is shown that minimal modifications to the algorithm will adapt it for use on shared memory architectures as well. r I u-,,