C-to-CoRAM: Compiling Perfect Loop Nests to the Portable CoRAM Abstraction

This paper presents initial work on developing a C compiler for the CoRAM FPGA computing abstraction. The pre-sented effort focuses on compiling fixed-bound perfect loop nests that operate on large data sets in external DRAM. As required by the CoRAM abstraction, the compiler partitions source code into two separate implementation components: (1) hardware kernel pipelines to be mapped onto the recon-figurable logic fabric; and (2) control threads that express, in a C-like language, the sequencing and coordination of data transfers between the hardware kernels and external DRAM. The compiler performs optimizations to increase parallelism and use DRAM bandwidth efficiently. It can target different FPGA platforms that support the CoRAM abstraction, either natively in a future FPGA or in soft-logic on today’s devices. The CoRAM abstraction provides a con-venient high-level compilation target to simplify the task of design optimization and system generation. The compiler is evaluated using three test programs (matrix-matrix mul-tiplication, k-nearest neighbor, and 2D convolution) on the Xilinx ML605 and the Altera DE4. Results show that our compiler is able to target the different platforms and effec-tively exploit their dissimilar capacities and features. De-pending on the application, the compiler-generated imple-mentations achieve performance ranging from a factor of 4 slower to a factor of 2 faster relative to hand-designed im-plementations, as measured on actual hardware