Dual Compilation for Hardware and Software

We show how a high level programming language like C may be used for hardware/software-codesign. Since the compilation for a software target is a well-known process, we have focus our discussion on the compilation for a hardware target. We start our work with the programming language proposed by Ian Page et. al. The first step is to figure out the deficiencies of this programming language (we call it the reference system in our discussion). We figure out that using the reference system prevents the developer from implementing time-accurate hardware designs. The reference design does not provide any constructs for explicit timing implementation. It assumes that all the statements at source code level use the same processing time. For this purpose we implement a steering mechanism for the timing. Many expert groups tried to generate silicon net lists from ANSI-C but these approaches lead to inefficient silicon. We try to find an optimal compromise between nearness to ANSI-C and the requirements for efficient silicon compilation. The second main innovation step is the implementation of an intermediate code. We show that this intermediate code enables the system to produce target designs with higher quality than the direct generation from the source code. An efficient intermediate code is essential for our system because we want to generate time-accurate systems. The intermediate code proposed in this document meets all the requirements for a precise and efficient timing. Its level of abstraction is high enough to hide the device specifics and low enough to avoid any additional processing except the routing and placing that is done by the software provided by the device vendors. The intermediate code is also suitable for high-performance optimizations, especially for timing optimizations. Common hardware and software design systems do not take care of the timing analysis during compilation time. The developers of these systems assume that the user measures the timing after the design is finished. This is done using simulators at early stages of the design. In later stages it may be done on the real target. If the design does not meet the requirements it will be refined. This design loop has to be repeated until the results meet the desired parameters. We try to go a different way and calculate the timing during compilation time. This, of course, is done at intermediate code level. Even if the intermediate code is device-independent, the result of the timing calculation is not. It depends on the particular hardware or software device that is used in the final target. For example, if we use an FPGA as a particular target the timing depends on one hand on the result of the placing and routing and on the other hand on the latencies of the particular implementation of the Boolean functions. The timing information is provided by the device vendor (i.e. the latencies of the different atomic design blocks.) A comparison to a similar work has shown that our approach has a lot of advantages. The main ones are: (i) Our algorithm can produce hardware and software from the same source code. (ii) Our algorithm can produce time-accurate designs. (iii) The designer is not burdened to take care of the synchronization of the different data paths. (iv) The optimization and refinement is done at a suitable stage - the intermediate code (a final optimization is also done at the assembler level or the net list level respectively). (v) It is not necessary to measure the timing after finishing the design, since it is calculated in the compilation process.Die Dissertation behandelt das Thema der Dualen Kompilierung, d.h. das Erstellen von Assembler-Code für einen Mikroprozessor ebenso wie das Generieren von Gatter-Netzlisten aus derselben Hochsprache. Als Programmiersprache wird die Sprache C in etwas abgewandelten Form benutzt; sie ist sehr ähnlich der Sprache Handel-C von Ian Page, Universität Oxford. Der Schwerpunkt liegt dabei auf der Generation der Netzlisten, da es hinlänglich bekannt ist, dass C eine geeignete Sprache zur Übersetzung in Assembler-Code ist. Die Arbeit kann grob in fünf Themen untergliedert werden: (i) Die Definition der Programmiersprache (ii) Die Formale Beschreibung des Zwischen-Codes (iii) Der Compiler selbst, sowie die benutzten Optimierungstechniken (iv) Experimentelle Ergebnisse (v) Die Einbettung der Arbeiten in andere verwandte Forschungsaktivitäte