Ecient Circuit Partitioning to Extend Cycle Simulation Beyond Synchronous Circuits

Cycle simulation techniques, such as levelized com-piled code, can ordinarily be applied only to synchronous designs. They usually cannot be applied to designs con-taining circuit features like combinational paths, multi-ple clock domains, generated clocks, asynchronous re-sets, and transparent latches. This paper presents a novel partitioning algorithm that partitions a non-cycle-simulatable circuit containing these features into sub-circuits that can be cycle simulated. Cycle simulation techniques can be applied to the individual sub-circuits, and the whole collection of sub-circuits can be simulated together using conventional co-simulation techniques. Empirical results demonstrate that this approach brings the benets of cycle simulation to circuits that were pre-viously impossible to cycle simulate. The partitioning algorithm requires time and space linear in the size of the circuit, and in practice is very fast. We also dis-cuss how the key ideas presented here can be applied to accelerate HDL simulation.