Add to ORKGThe partitioning of complex processor models on the gate and register-transfer level for parallel functional simulation based on the clock-cycle algorithm is considered. We introduce a hierarchical partitioning scheme combining various partitioning algorithms in the frame of a competing strategy. Melting together different partitioning results within one level using superpositions we crossover to a mixture of experts one. This approach is improved applying genetic algorithms. In addition we present two new partitioning algorithms both of them taking cones as fundamental units for building partitions
Cycle simulation techniques, such as levelized com-piled code, can ordinarily be applied only to syn...
One approach to accelerate a simulation of digital circuits described in VHDL is a distributed simul...
We demonstrate circuits that generate set and integer partitions on a set S of n objects at a rate o...
The partitioning of complex processor models on the gate and register-transfer level for parallel fu...
The partitioning of complex processor models on the gate and register-transfer level for parallel fu...
Parallelization of VLSI-simulation exploiting model-inherent parallelism is a promising way to accel...
The application of Evolutionary Algorithms in hierarchical model partitioning for parallel system si...
Parallelization of logic simulation on register-transfer and gate level is a promising way to accele...
Parallelization of logic simulation on register-transfer and gate level is a promising way to accele...
Distributing simulations among multiple processors is one approach to reducing VHDL simulation time ...
Partitioning is a critical area of VLSI CAD. In order to build complex digital logic circuits its of...
Eine wichtige Form der Verifkation von komplette Prozessorstrukturen umfassenden VLSI-Entwürfen stel...
Circuit simulation is an indispensable tool in the design and analysis of Very Large Scale Integrate...
Logic simulation is a crucial verification task in processor design. Aiming at significant accelerat...
As a consequence of Moore's law, the size of integrated circuits has grown extensively, resulting in...
Cycle simulation techniques, such as levelized com-piled code, can ordinarily be applied only to syn...
One approach to accelerate a simulation of digital circuits described in VHDL is a distributed simul...
We demonstrate circuits that generate set and integer partitions on a set S of n objects at a rate o...
The partitioning of complex processor models on the gate and register-transfer level for parallel fu...
The partitioning of complex processor models on the gate and register-transfer level for parallel fu...
Parallelization of VLSI-simulation exploiting model-inherent parallelism is a promising way to accel...
The application of Evolutionary Algorithms in hierarchical model partitioning for parallel system si...
Parallelization of logic simulation on register-transfer and gate level is a promising way to accele...
Parallelization of logic simulation on register-transfer and gate level is a promising way to accele...
Distributing simulations among multiple processors is one approach to reducing VHDL simulation time ...
Partitioning is a critical area of VLSI CAD. In order to build complex digital logic circuits its of...
Eine wichtige Form der Verifkation von komplette Prozessorstrukturen umfassenden VLSI-Entwürfen stel...
Circuit simulation is an indispensable tool in the design and analysis of Very Large Scale Integrate...
Logic simulation is a crucial verification task in processor design. Aiming at significant accelerat...
As a consequence of Moore's law, the size of integrated circuits has grown extensively, resulting in...
Cycle simulation techniques, such as levelized com-piled code, can ordinarily be applied only to syn...
One approach to accelerate a simulation of digital circuits described in VHDL is a distributed simul...
We demonstrate circuits that generate set and integer partitions on a set S of n objects at a rate o...