PARALLEL SWITCH-LEVEL SIMULATION of VLSI CIRCUITS

This paper presents the results of an experimental study to evaluate the effectiveness of parallel simulation in reducing the execution time of switch-level models of VLSI circuits. Specific contributions of this paper include: (i)Parallelization of an existing switch-level simulator such that it can be executed with a variety of simulation protocols (almost all previous parallel circuit simulators have focused on gate-level models and have targeted either conservative or optimistic simulators, but not both). (ii) Adapting existing circuit partitioning algorithms designed for gate-level models to switch-level designs and evaluating their effectiveness for parallel simulation. (iii) Demonstrating speedups with both conservative and optimistic simulation protocols for a set of combinational circuits (almost all previous studies on parallel simulation for VLSI circuits have failed to extract speedups with conservative protocols); in particular our experiments showed that it was possible t..