An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions

Current superscalar processors use a Reorder Buffer (ROB) to support speculation, precise exceptions, and reg-ister reclamation. Instructions are retired from this struc-ture in program order, which may lead to significant perfor-mance degradation if a long latency operation blocks the ROB head. In this paper, a checkpoint-free out-of-order commit architecture is proposed, which replaces the ROB with a small structure called Validation Buffer (VB) from which instructions are retired as soon as their speculative state is resolved. An aggressive register reclamation mech-anism targeted to this microarchitecture is also devised. Ex-perimental results show that the VB microarchitecture is much more efficient than a ROB-based microprocessor. For example, a 32-entry VB provides similar performance to a 256-entry ROB, while reducing the utilization of other ma-jor processor structures.