Exploiting short-lived variables in superscalar processors

Modern superscalar processors use advanced features like dynamic scheduling and speculative execution to exploit fine-grain parallelism. In order to support these features, they use complex hardware mechanisms like reorder buffers, instructions windows and renaming buffers. In this thesis, we have made an observation about the use of these mechanisms: a significant number of program variables are short-lived in the sense that their whole live ranges occur entirely within the reorder buffer. Therefore, the values produced by these short-lived variables do not need to be written back (committed) to the register file. Based on this observation, we have proposed a compiler analysis, which we call short-live-range analysis, and a simple architecture feature to avoid the useless commits of the values generated by these short-lived variables. Moreover, we have proposed a new register allocation scheme to assign these variables to the locations provided for register renaming (rather than to the register file), thus decreasing the register pressure.We have implemented his hardware/software codesign scheme using the McCAT testbed and the simulation results show: (1) the short-live-range analysis and the proposed architecture feature can be successfully used to avoid the useless commit of instructions to the register files; (2) the above mechanism can reduce the number of write ports to the register files without affecting performance; (3) the allocation of short-lived variables to the locations provided by the register files without affecting performance; (3) the allocation of short-lived variables to the locations provided by the register renaming mechanism can significantly reduce the introduction of spill code and improve the overall performance