Caching is a well-known technique for speeding up com-putation. We cache data from file systems and databases; we cache dynamically generated code blocks; we cache page translations in TLBs. We propose to cache the act of com-putation, so that we can apply it later and in different con-texts. We use a state-space model of computation to sup-port such caching, involving two interrelated parts: spec-ulatively memoized predicted/resultant state pairs that we use to accelerate sequential computation, and trained proba-bilistic models that we use to generate predicted states from which to speculatively execute. The key techniques that make this approach feasible are designing probabilistic mod-els that automatically focus on regions of program e...
An ideal high performance computer includes a fast processor and a multi-million byte memory of comp...
Cache performance is critical in cache-based supercomputers, where the cache-miss/cache-hit memory r...
For many programs, especially integer codes, untolerated load instruction latencies account for a si...
Caching is a well-known technique for speeding up computation. We cache data from file systems and d...
It has been claimed that the execution time of a program can often be predicted more accurately on a...
Modern processors rely heavily on speculation to provide performance. Techniques such as branch pred...
Cache behavior is complex and inherently unstable, yet it is a critical factor affecting program per...
We present a cache performance modeling methodology that facilitates the tuning of uniprocessor cach...
This thesis presents a generic approach towards compiling fast execution-driven simulators, and appl...
This paper presents a generic approach for compiling fast execution-driven simulators, and applies t...
We present a novel, compile-time method for determining the cache performance of the loop nests in a...
This paper describes the design, implementation, and evaluation of a predictive file caching approac...
Speculative parallelization aggressively runs hard-to-analyze codes in parallel. Speculative tasks g...
. The main contributions of this paper are twofold. First, a general framework for control-flow part...
Dependences among loads and stores whose addresses are unknown hinder the extraction of instruction ...
An ideal high performance computer includes a fast processor and a multi-million byte memory of comp...
Cache performance is critical in cache-based supercomputers, where the cache-miss/cache-hit memory r...
For many programs, especially integer codes, untolerated load instruction latencies account for a si...
Caching is a well-known technique for speeding up computation. We cache data from file systems and d...
It has been claimed that the execution time of a program can often be predicted more accurately on a...
Modern processors rely heavily on speculation to provide performance. Techniques such as branch pred...
Cache behavior is complex and inherently unstable, yet it is a critical factor affecting program per...
We present a cache performance modeling methodology that facilitates the tuning of uniprocessor cach...
This thesis presents a generic approach towards compiling fast execution-driven simulators, and appl...
This paper presents a generic approach for compiling fast execution-driven simulators, and applies t...
We present a novel, compile-time method for determining the cache performance of the loop nests in a...
This paper describes the design, implementation, and evaluation of a predictive file caching approac...
Speculative parallelization aggressively runs hard-to-analyze codes in parallel. Speculative tasks g...
. The main contributions of this paper are twofold. First, a general framework for control-flow part...
Dependences among loads and stores whose addresses are unknown hinder the extraction of instruction ...
An ideal high performance computer includes a fast processor and a multi-million byte memory of comp...
Cache performance is critical in cache-based supercomputers, where the cache-miss/cache-hit memory r...
For many programs, especially integer codes, untolerated load instruction latencies account for a si...