Using Static Program Analysis to Compile Fast Cache Simulators

This paper presents a generic approach for compiling fast execution-driven simulators, and applies the approach to simulating the effects of program execution in computer hardware. Our approach is based on using static program analysis to guide partial evaluation and slicing of simula-tors. Because results of some simulation operations are known before execution, a cache simulator program can be partially evaluated during its compilation. Program slicing can be used to remove the computations that have no effect on the simulation result. Our experimental work with cache analysis shows that our approach significantly speeds up simulations. Fast cache simulation is needed in development of both computer soft-ware and hardware. To properly understand the cache be-havior caused by a computer program, simulations must be done with sufficiently many inputs. Traditional simulation of memory operations caused by a computer program can be orders of magnitude slower than execution of the pro-gram. Our approach reduces the time needed in cache per-formance evaluations without losing accuracy of the results