This thesis presents a generic approach towards compiling fast execution-driven simulators, and applies this to cache simulation of programs. The resulting cache simulation method reduces the time needed for cache performance evaluations without losing the accuracy of the results. Fast cache simulators are needed in the performance analysis of software systems. To properly understand the cache behavior caused by a program, simulations must be performed with a sufficient number of inputs. Traditional simulation of memory operations of a program can be orders of magnitude slower than the execution of the program. This leads to simulation times that are often infeasible in software development. The approach of this thesis is based on using s...
An application’s cache miss rate is used in timing analysis, system performance prediction and ...
We present an extension to an existing SPARC V8 in-struction set simulator, SimICS, to support accur...
The use of caches poses a difficult tradeoff for architects of real-time systems. While caches provi...
This thesis presents a generic approach towards compiling fast execution-driven simulators, and appl...
This paper presents a generic approach for compiling fast execution-driven simulators, and applies t...
. The main contributions of this paper are twofold. First, a general framework for control-flow part...
Application-specific system-on-chip platforms create the opportu-nity to customize the cache configu...
It has been claimed that the execution time of a program can often be predicted more accurately on a...
We describe novel techniques used for efficient simulation of memory in SimICS, an instruction level...
Abstract- Cache memory performance analysis is a challenging topic upon first introduction. Students...
We describe novel techniques used for efficient simulation of memory in SimICS, an instruction leve...
Techniques to evaluate a program’s cache performance fall into two camps: 1. Traditional trace-base...
We present a novel, compile-time method for determining the cache performance of the loop nests in a...
Parallelism is everywhere, with co-processors such as Graphics Processing Units (GPUs) accelerating ...
Application performance on computer processors depends on a number of complex architectural and micr...
An application’s cache miss rate is used in timing analysis, system performance prediction and ...
We present an extension to an existing SPARC V8 in-struction set simulator, SimICS, to support accur...
The use of caches poses a difficult tradeoff for architects of real-time systems. While caches provi...
This thesis presents a generic approach towards compiling fast execution-driven simulators, and appl...
This paper presents a generic approach for compiling fast execution-driven simulators, and applies t...
. The main contributions of this paper are twofold. First, a general framework for control-flow part...
Application-specific system-on-chip platforms create the opportu-nity to customize the cache configu...
It has been claimed that the execution time of a program can often be predicted more accurately on a...
We describe novel techniques used for efficient simulation of memory in SimICS, an instruction level...
Abstract- Cache memory performance analysis is a challenging topic upon first introduction. Students...
We describe novel techniques used for efficient simulation of memory in SimICS, an instruction leve...
Techniques to evaluate a program’s cache performance fall into two camps: 1. Traditional trace-base...
We present a novel, compile-time method for determining the cache performance of the loop nests in a...
Parallelism is everywhere, with co-processors such as Graphics Processing Units (GPUs) accelerating ...
Application performance on computer processors depends on a number of complex architectural and micr...
An application’s cache miss rate is used in timing analysis, system performance prediction and ...
We present an extension to an existing SPARC V8 in-struction set simulator, SimICS, to support accur...
The use of caches poses a difficult tradeoff for architects of real-time systems. While caches provi...